Stack-type capacitor, semiconductor memory device having the same, and methods of manufacturing the capacitor and the semiconductor memory device

ABSTRACT

A stack-type capacitor includes a lower electrode, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, wherein the lower electrode includes a first metal layer having a cylindrical shape and a second metal layer filled in the first metal layer. In the capacitor, an amount of oxygen included in the lower electrode is decreased to suppress oxidation of a TiN layer. Thus, a stable stack-type capacitor may be formed, which increases greatly the performance of highly integrated DRAMs.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a stack-type capacitor in whicha lower electrode is formed of two different metal layers, asemiconductor memory device including the stack-type capacitor, andmethods of manufacturing the capacitor and the semiconductor memorydevice.

[0003] 2. Description of the Related Art

[0004] As the area occupied by a memory cell is scaled down, cellcapacitance decreases. A decrease in the cell capacitance is typically aserious obstacle in increasing the integration density of dynamic randomaccess memory (DRAM) devices. In a memory device, a decrease in the cellcapacitance not only lowers the ability to read a memory cell andincreases a soft error rate, but also hinders the operation of a deviceat a low voltage. Therefore, a method for increasing cell capacitance isneeded for the manufacture of a highly integrated semiconductor memorydevice.

[0005] In order to increase a cell capacitance, cylindrical electrodesare used to increase the area of electrodes.

[0006]FIG. 1 illustrates a schematic cross-sectional view of aconventional cylindrical capacitor.

[0007] Referring to FIG. 1, an interlayer dielectric (ILD) 11 and anetch stop layer 12 are deposited on a substrate 20, and are patterned toform a contact hole 11 a. The contact hole 11 a is filled with aconductive plug 13. A lower electrode 14 is formed in a cylindricalshape over the conductive plug 13. A dielectric layer 15 and an upperelectrode 16 are sequentially deposited on the lower electrode 14.

[0008] The electrodes of the cylindrical capacitor have increased areas,and the cylindrical capacitor has an improved capacitance. The prior artincludes a method of manufacturing a cylindrical capacitor in which ahemispherical grain (HSG) is grown on an exposed portion of acylindrical structure to increase the areas of electrodes.

[0009] However, in a highly integrated memory device using thisconventional cylindrical capacitor, the inside of a hollow cylindricalstructure is so narrow that inner walls may contact each other. To solvethis problem, a filled cylindrical stack-type capacitor (hereinafter,referred to as a “stack-type capacitor”) occupying a narrow area isrequired. Since the sectional area of the stack-type capacitor issmaller than that of a cylindrical capacitor, the integration density ofa memory device may be improved.

[0010]FIG. 2 illustrates a cross-sectional view of a DRAM cell includinga stack-type capacitor having a ruthenium (Ru) electrode.

[0011] Referring to FIG. 2, the DRAM cell includes a stack-typecapacitor 40 and a switching transistor 30. The transistor 30 includesan n⁺-type source region 21 and an n⁺-type drain region 22, which areformed to be spaced apart from each other in a surface of a substrate 20formed of p-type silicon. A gate insulating layer 31 and a gateelectrode 32 are formed on the substrate 20 between the source region 21and the drain region 22.

[0012] The stack-type capacitor 40 is formed on the transistor 30 via aninterlayer dielectric (ILD) 33. To form the stack-type capacitor 40, alower electrode 41, a dielectric layer 43, and an upper electrode 44 aresequentially stacked on the ILD 33. The lower electrode 41 and the upperelectrode 44 are formed of ruthenium, and a dielectric material 42, suchas Ta₂O₅, is filled in the lower electrode 41. The source region 21 ofthe transistor 30 is electrically connected to the lower electrode 41 ofthe capacitor 40 by a contact hole 33 a formed in the ILD 33. Thecontact hole 33 a is filled with a conductive plug 34 formed ofpolysilicon or tungsten. Also, a conductive barrier layer, e.g., a TiNlayer 35, is formed between the conductive plug 34 and the lowerelectrode 41. The conductive barrier layer 35 is a diffusion barrierlayer that prevents mutual diffusion or chemical reactions between theconductive plug 34 and the lower electrode 41. Although it is possibleto use a TaN layer or a WN layer, the TiN layer 35 is generally used.The TiN layer 35 isolates the lower electrode 41 from the conductiveplug 34, thereby preventing diffusion from the conductive plug 34 intothe lower electrode 41 and exposure of the conductive plug 34 to oxygenduring deposition. Reference numeral 45 denotes an etch stop layer to bedescribed later.

[0013] This stack-type capacitor of FIG. 2, which takes up a smallerarea than the conventional cylindrical capacitor of FIG. 1, is moreappropriate for a highly integrated memory device.

[0014]FIGS. 3A through 3E illustrate cross-sectional views for showing amethod of manufacturing a semiconductor memory device including thestack-type capacitor of FIG. 2.

[0015] A transistor 30 is formed on a semiconductor substrate 20 by aknown semiconductor manufacturing method. Next, a first ILD 33 is formedon the semiconductor substrate 20. The first ILD 33 is selectivelyetched to form a contact hole 33 a, which exposes a source region 21 ofthe transistor 30. The contact hole 33 a is filled with a conductiveplug 34 to connect the conductive plug 34 with the source region 21, asshown in FIG. 3A.

[0016] Thereafter, an insulating layer 36 is formed on the first ILD 33to cover the conductive plug 34. The insulating layer 36 is selectivelyetched to expose the conductive plug 34. A TiN layer 35 is deposited bychemical vapor deposition (CVD) on the insulating layer 36 and thenplanarized by chemical mechanical polishing (CMP) until the insulatinglayer 36 and the TiN layer 35 are exposed, as shown in FIG. 3B.

[0017] Thereafter, a SiN etch stop layer 45 and a SiO₂ second ILD 46 aresequentially stacked on the insulating layer 36 and the TiN layer 35 andthen etched by a dry etch process until a portion of the TiN layer 35 isexposed, thereby forming a via hole 46 a. An electrode of the capacitorwill be formed in the via hole 46 a and on the portion of the TiN layer35 exposed by the via hole 46 a. Next, a conductive layer 41, e.g., a Rulayer, is formed by CVD to cover the entire surface of the TiN layer 35exposed by the via hole 46 a, and a Ta₂O₅ layer 42 is formed thereon(refer to FIG. 3C).

[0018] Next, the resultant structure is planarized by CMP until thesecond ILD 46 is exposed, and the second ILD 46 is etched by a Hf wetetch process to form a stack-type lower electrode 41 (refer to FIG. 3D).

[0019] Next, a dielectric layer 43 and a Ru upper electrode 44 aresequentially formed on the lower electrode 41, and eventually astack-type capacitor 40 is completed (refer to FIG. 3E).

[0020] However, in this method, when the lower electrode 41 is formed bydepositing a Ru layer using CVD, since oxygen is used for a reactiongas, the TiN layer 35 connected to the lower electrode 41 is oxidizedand thus volumetrically expands. The volumetric expansion of the TiNlayer 35 causes a vacancy between the TiN layer 35 and the Ru lowerelectrode 41, as shown in the photograph of FIG. 4. Thus, the stack-typecapacitor including the Ru lower electrode does not resist andcollapses. As shown in FIG. 5, a photograph taken of a storage nodeshows that a capacitor leans toward and contacts the next capacitor.This degrades electrical properties of the capacitor, thus increasingleakage current.

SUMMARY OF THE INVENTION

[0021] In an effort to solve these and other problems, the presentinvention provides a stack-type capacitor including a lower electrodethat is formed of two different metals and has improved physicalproperties and a semiconductor memory device having the same.

[0022] The present invention also provides methods of manufacturing thestack-type capacitor and the semiconductor memory device including thecapacitor.

[0023] Accordingly, it is a feature of a first embodiment of the presentinvention to provide a stack-type capacitor including a lower electrode,a dielectric layer formed on the lower electrode, and an upper electrodeformed on the dielectric layer, wherein the lower electrode includes afirst metal layer having a cylindrical shape and a second metal layerfilled in the first metal layer.

[0024] The first metal layer may be a ruthenium (Ru) layer and thesecond metal layer may be a nitride and aluminum layer. The nitride andaluminum layer may be a titanium aluminum nitride (TiAlN) layer or atantalum aluminum nitride layer.

[0025] The upper electrode may be a ruthenium (Ru) layer.

[0026] It is another feature of an embodiment of the present inventionto provide a semiconductor memory device including a stack-typecapacitor, the device including a transistor and a capacitor, whereinthe capacitor includes a lower electrode, a dielectric layer formed onthe lower electrode, and an upper electrode formed on the dielectriclayer, wherein the lower electrode includes a first metal layer having acylindrical shape and a second metal layer filled in the first metallayer.

[0027] The transistor may be electrically connected to the capacitor bya conductive plug, and a diffusion barrier layer, i.e., a TiN layer, maybe formed between the lower electrode and the conductive plug.

[0028] It is a third feature of an embodiment of the present inventionto provide a method of manufacturing a stack-type capacitor, the methodincluding (a) sequentially stacking an etch stop layer and an ILD on asubstrate and forming a via hole by patterning the ILD and the etch stoplayer, (b) sequentially forming a first metal layer and a second metallayer on the via hole and the ILD, (c) exposing the ILD, (d) forming alower electrode formed of the first metal layer and the second metallayer by removing the ILD, and (e) sequentially depositing a dielectriclayer and an upper electrode on the lower electrode, wherein the firstmetal layer is formed by atomic layer deposition.

[0029] The first metal layer may be formed of ruthenium and the secondmetal layer may be formed of titanium aluminum nitride or tantalumaluminum nitride. The upper electrode may be formed of ruthenium.

[0030] Step (b) may include absorbing a Ru precursor to a resultantstructure of step (a), purging any remaining Ru precursor, decomposingthe Ru precursor by absorbing an oxygen gas to the absorbed Ru precursorlayer to form a ruthenium oxide layer, purging any remaining oxygen gas,and reducing the ruthenium oxide layer by supplying a hydrogen gasthereto.

[0031] Before absorbing the Ru precursor, the method may furthercomprise absorbing iodine (I), which is a halogen-series material, tothe resultant structure of step (a).

[0032] It is a third feature of an embodiment of the present inventionto provide a method of manufacturing a semiconductor memory deviceincluding a stack-type capacitor, the method including (a) forming atransistor on a substrate, (b) forming a first ILD on the substrate, (c)forming a contact hole in the first ILD to expose a predetermined regionof the transistor, (d) forming a conductive plug in the contact hole,(e) forming an insulating layer on the first ILD, patterning theinsulating layer until the conductive plug is exposed, and forming adiffusion barrier layer on the exposed portion, (f) sequentiallystacking an etch stop layer and a second ILD on the first ILD andpatterning the second ILD and the etch stop layer to expose thediffusion barrier layer (g) sequentially forming a first metal layer anda second metal layer on a resultant structure of step (f), (h) exposingthe second ILD, (i) forming a lower electrode formed of the first metallayer and the second metal layer by removing the second ILD, and (j)sequentially depositing a dielectric layer and an upper electrode on thelower electrode, wherein the first metal layer is formed by atomic layerdeposition.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other features and advantages of the presentinvention will become more apparent to those of ordinary skill in theart by describing in detail preferred embodiments thereof with referenceto the attached drawings in which:

[0034]FIG. 1 illustrates a schematic cross-sectional view of aconventional cylindrical capacitor;

[0035]FIG. 2 illustrates a cross-sectional view of a DRAM cell includinga stack-type capacitor having Ru electrodes;

[0036]FIGS. 3A through 3E illustrate cross-sectional views for showing amethod of manufacturing a semiconductor memory device including thestack-type capacitor as shown in FIG. 2;

[0037]FIG. 4 is a microscopic photograph of a lower electrode includingan oxidized TiN layer;

[0038]FIG. 5 is a microscopic photograph of a storage node in which acapacitor leans toward and contacts the next capacitor;

[0039]FIG. 6 illustrates a cross-sectional view of a DRAM cell includinga stack-type capacitor according to an embodiment of the presentinvention;

[0040]FIG. 7 illustrates a graph showing activity of TiN in an oxidizedatmosphere depending on whether or not Al is added to TiN; and

[0041]FIGS. 8A through 8F illustrate cross-sectional views for showing amethod of manufacturing a semiconductor memory device including thestack-type capacitor as shown in FIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

[0042] Korean Patent Application No. 2003-32255, filed on May 21, 2003,and entitled: “Stack-Type Capacitor, Semiconductor Memory Device HavingThe Same, And Methods Of Manufacturing The Capacitor And TheSemiconductor Memory Device,” is incorporated by reference herein in itsentirety.

[0043] The present invention will now be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. The invention may,however, be embodied in different forms and should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. In the drawings, the thickness of layers and regions areexaggerated for clarity. It will also be understood that when a layer isreferred to as being “on” another layer or substrate, it can be directlyon the other layer or substrate, or intervening layers may also bepresent. Further, it will be understood that when a layer is referred toas being “under” another layer, it can be directly under, and one ormore intervening layers may also be present. In addition, it will alsobe understood that when a layer is referred to as being “between” twolayers, it can be the only layer between the two layers, or one or moreintervening layers may also be present. Like numbers refer to likeelements throughout.

[0044]FIG. 6 illustrates a cross-sectional view of a DRAM cell includinga stack-type capacitor according to an embodiment of the presentinvention.

[0045] Referring to FIG. 6A, the memory device includes a stack-typecapacitor 140 and a switching transistor 130. The transistor 130includes an n⁺-type source region 121 and an n⁺-type drain region 122,which are formed to be spaced apart from each other on a substrate 120formed of p-type silicon. A gate insulating layer 131 and a gateelectrode 132 as a word line are formed on the substrate 120 between thesource region 121 and the drain region 122.

[0046] A stack-type capacitor 140 is formed on the transistor 130 via afirst interlayer dielectric (ILD) 133. In order to form the stack-typecapacitor 140, a lower electrode 141, a dielectric layer 143, and anupper electrode 144 are sequentially stacked on the first ILD 133. Thelower electrode 141 includes a cylindrical Ru layer 141 a and a TiAlNlayer (or a TaAlN layer) 141 b filled in the Ru layer 141 a. The upperelectrode 144 is formed of Ru. The source region 121 of the transistor130 is electrically connected to the lower electrode 141 of thecapacitor 140 by a contact hole 133 a formed in the first ILD 133. Thecontact hole 133 a is filled with a conductive plug 134 formed ofpolysilicon or tungsten. Also, a conductive barrier layer, e.g., a TiNlayer 135, which is a diffusion barrier layer preventing mutualdiffusion or chemical reactions between different materials, is formedbetween the conductive plug 134 and the lower electrode 141. Although itis possible to use a TaN layer or a WN layer, the TiN layer 135 isgenerally used. The TiN layer 135 isolates the lower electrode 141 fromthe conductive plug 134, thereby preventing diffusion from theconductive plug 134 into the lower electrode 141 and exposure of theconductive plug 134 to oxygen during deposition. Reference numeral 145denotes an etch stop layer.

[0047] In the present invention, the lower electrode 141 is formed ofTiAlN to solve structural instability of a capacitor due to oxidation ofTiN 135. That is, as shown in FIG. 7, TiAlN shows a larger activity thanTiN in an oxidized atmosphere. Since Al is oxidized earlier than TiN, apartial pressure of oxygen is lowered by the addition of the Al, andoxidation of the TiN is delayed. That is, Al leads a reduced amount ofoxygen to react on TiN, thus suppressing oxidation of TiN.

[0048] Also, Ru for the lower electrode 141 is deposited by atomic layerdeposition (ALD). The ALD process is a thin-film deposition techniqueusing chemical absorption and desorption of a monatomic layer. In theALD process, reactants are individually separated and supplied to achamber in a pulsed mode such that the reactants are deposited on thesurface of a substrate by chemical absorption and desorption due to asaturated surface reaction. Meanwhile, a halogen-series material, suchas iodine (I), is firstly absorbed on a substrate, where a Ru layer isto be deposited, and then a Ru precursor is absorbed such that theiodine induces decomposition of the Ru precursor. Next, an oxygen gas isabsorbed on the Ru precursor layer. Thus, a ligand of the Ru precursorreacts on oxygen and decomposes. The decomposed Ru is oxidized togenerate ruthenium oxide. Next, hydrogen is absorbed on the resultantstructure and reduces the ruthenium oxide, thereby removing oxygenincluded in Ru. As a result, oxidation between TiN and Ru, which is usedfor the lower electrode 141, may be suppressed.

[0049]FIGS. 8A through 8F illustrate cross-sectional views for showing amethod of manufacturing a semiconductor memory device including thestack-type capacitor as shown in FIG. 6.

[0050] A transistor 130 is formed on a semiconductor substrate 120 by aknown semiconductor manufacturing method. Next, a first ILD 133 isformed on the semiconductor substrate 120. The first ILD 133 isselectively etched to form a contact hole 133 a, thereby exposing asource region 121 of the transistor 130. Then, the contact hole 133 a isfilled with a conductive plug 134 to connect the conductive plug 134with the source region 121 as shown in FIG. 8A.

[0051] Thereafter, an insulating layer 136 is formed on the first ILD133 to cover the conductive plug 134. The insulating layer 136 isselectively etched until the conductive plug 134 is exposed. Next, a TiNlayer 135 is deposited by CVD on the insulating layer 136 and planarizedby CMP until the insulating layer 136 is exposed, thereby forming theTiN layer 135 as illustrated in FIG. 8B.

[0052] Thereafter, a SiN etch stop layer 145 and a SiO₂ second ILD 146are sequentially stacked on the insulating layer 136 and the TiN layer135. The SiN etch stop layer 145 and SiO₂ second ILD 146 are etchedusing a dry etch process until the TiN layer 135 is exposed, therebyforming a via hole 146 a as shown in FIG. 8C. The via hole 146 a exposesa region where a capacitor electrode will be formed.

[0053] A process of forming a Ru layer 141 a for a lower electrode 141on the via hole 146 a using ALD will now be described. First, ahalogen-series material, e.g., iodine, is absorbed on the insulatinglayer 146 and in the via hole 146 a. The halogen-series material reactson a Ru precursor, which will be used in a subsequent ALD process, andinduces decomposition of the Ru precursor. The Ru precursor is absorbedon the entire surface of the insulating layer 146 where the iodine isabsorbed, to cover the entire exposed surface of the TiN layer 135.Here, the iodine absorbed on the insulating layer 146 reacts on the Ruprecursor and decomposes Ru from a ligand. Then, any remaining Ruprecursor is purged. Next, an oxygen gas is absorbed on the Ru precursorlayer. The oxygen gas reacts on the ligand of the Ru precursor anddecomposes the Ru precursor, and the decomposed Ru reacts on oxygen,thus generating ruthenium oxide. Then, the oxygen gas is purged.Thereafter, a hydrogen gas is absorbed such that a reaction betweenoxygen and hydrogen occurs, thus generating water vapor. As a result,the amount of oxygen included in the ruthenium oxide is significantlydecreased. By repeating the foregoing steps, the Ru layer 141 a having apredetermined thickness is deposited on the via hole 146 a and thesecond ILD 146.

[0054] Thereafter, a TiAlN layer (or a TaAlN layer) 141 b is depositedby CVD or ALD on the Ru layer 141 a as shown in FIG. 8D.

[0055] Next, the Ru layer 141 a and the TiAlN layer 141 b are planarizedby CMP until the insulating layer 146 is exposed. The second ILD 146 isetched using a Hf wet etch process, thereby forming a stack-type lowerelectrode 141 as shown in FIG. 8E.

[0056] Next, a dielectric layer 143 and a Ru upper electrode layer 144are sequentially formed on the lower electrode 141 and eventually astack-type capacitor 140 is completed as shown in FIG. 8F. Thedielectric layer 143 is formed of HfO₂, Ta, TiO₂, or BST.

[0057] As explained thus far, in the present invention, an amount ofoxygen in a lower electrode is decreased, thereby suppressing oxidationof a TiN layer. Thus, a stable stack-type capacitor may be formed, whichgreatly increases the performance of highly integrated DRAMs.

[0058] Preferred embodiments of the present invention have beendisclosed herein and, although specific terms are employed, they areused and are to be interpreted in a generic and descriptive sense onlyand not for purpose of limitation. Accordingly, it will be understood bythose of ordinary skill in the art that various changes in form anddetails may be made without departing from the spirit and scope of thepresent invention as set forth in the following claims.

What is claimed is:
 1. A stack-type capacitor comprising: a lowerelectrode; a dielectric layer formed on the lower electrode; and anupper electrode formed on the dielectric layer, wherein the lowerelectrode includes: a first metal layer having a cylindrical shape; anda second metal layer filled in the first metal layer.
 2. The capacitoras claimed in claim 1, wherein the first metal layer is a rutheniumlayer and the second metal layer is a nitride and aluminum layer.
 3. Thecapacitor as claimed in claim 2, wherein the nitride and aluminum layeris a titanium aluminum nitride layer or a tantalum aluminum nitridelayer.
 4. The capacitor as claimed in claim 2, wherein the upperelectrode is a ruthenium layer.
 5. A semiconductor memory deviceincluding a stack-type capacitor, the device comprising a transistor anda capacitor, wherein the capacitor includes: a lower electrode; adielectric layer formed on the lower electrode; and an upper electrodeformed on the dielectric layer, wherein the lower electrode includes: afirst metal layer having a cylindrical shape; and a second metal layerfilled in the first metal layer.
 6. The device as claimed in claim 5,wherein the transistor is electrically connected to the capacitor by aconductive plug.
 7. The device as claimed in claim 6, wherein adiffusion barrier layer is formed between the lower electrode and theconductive plug.
 8. The device as claimed in claim 7, wherein thediffusion barrier layer is a titanium nitride layer.
 9. The device asclaimed in claim 5, wherein the first metal layer is a ruthenium layer,and the second metal layer is a nitride and aluminum layer.
 10. Thedevice as claimed in claim 9, wherein the nitride and aluminum layer isa titanium aluminum nitride layer or a tantalum aluminum nitride layer.11. The device as claimed in claim 9, wherein the upper electrode is aruthenium layer.
 12. A method of manufacturing a stack-type capacitor,the method comprising: (a) sequentially stacking an etch stop layer andan interlayer dielectric on a substrate and forming a via hole bypatterning the interlayer dielectric and the etch stop layer; (b)sequentially forming a first metal layer and a second metal layer in thevia hole and on the interlayer dielectric; (c) exposing the interlayerdielectric; (d) forming a lower electrode formed of the first metallayer and the second metal layer by removing the interlayer dielectric;and (e) sequentially depositing a dielectric layer and an upperelectrode on the lower electrode, wherein the first metal layer isformed by atomic layer deposition.
 13. The method as claimed in claim12, wherein the first metal layer is formed of ruthenium and the secondmetal layer is formed of titanium aluminum nitride or tantalum aluminumnitride.
 14. The method as claimed in claim 13, wherein the upperelectrode is formed of ruthenium.
 15. The method as claimed in claim 12,wherein (b) includes: absorbing a ruthenium precursor to a resultantstructure of (a); purging any remaining ruthenium precursor; decomposingthe ruthenium precursor by absorbing an oxygen gas to the absorbedruthenium precursor layer, to thereby form a ruthenium oxide layer;purging any remaining oxygen gas; and reducing the ruthenium oxide layerby supplying a hydrogen gas thereto.
 16. The method as claimed in claim15, further comprising absorbing a halogen-series material to theresultant structure of (a) before absorbing the ruthenium precursor. 17.The method as claimed in claim 16, wherein the halogen-series materialis iodine.
 18. A method of manufacturing a semiconductor memory deviceincluding a stack-type capacitor, the method comprising: (a) forming atransistor on a substrate; (b) forming a first interlayer dielectric onthe substrate; (c) forming a contact hole in the first interlayerdielectric to expose a predetermined region of the transistor; (d)forming a conductive plug in the contact hole; (e) forming an insulatinglayer on the first interlayer dielectric, patterning the insulatinglayer until the conductive plug is exposed, and forming a diffusionbarrier layer on the exposed portion; (f) sequentially stacking an etchstop layer and a second interlayer dielectric on the first interlayerdielectric and patterning the second interlayer dielectric and the etchstop layer to expose the diffusion barrier layer; (g) sequentiallyforming a first metal layer and a second metal layer on a resultantstructure of (f); (h) exposing the second interlayer dielectric; (i)forming a lower electrode formed of the first metal layer and the secondmetal layer by removing the second interlayer dielectric; and (j)sequentially depositing a dielectric layer and an upper electrode on thelower electrode, wherein the first metal layer is formed by atomic layerdeposition.
 19. The method as claimed in claim 18, wherein the firstmetal layer is formed of ruthenium and the second metal layer is formedof titanium aluminum nitride.
 20. The method as claimed in claim 19,wherein the upper electrode is formed of ruthenium.
 21. The method asclaimed in claim 18, wherein the diffusion barrier layer is formed oftitanium nitride.
 22. The method as claimed in claim 21, wherein (g)includes: absorbing a ruthenium precursor on a resultant structure of(f); purging any remaining ruthenium precursor; decomposing theruthenium precursor by absorbing an oxygen gas to the absorbed rutheniumprecursor layer, to form a ruthenium oxide layer; purging any remainingoxygen gas; and reducing the ruthenium oxide layer by supplying ahydrogen gas thereto.
 23. The method as claimed in claim 22, furthercomprising absorbing a halogen-series material to the resultantstructure of (f) before absorbing the ruthenium precursor.
 24. Themethod as claimed in claim 23, wherein the halogen-series material isiodine.